RTL Verification Engineer--AI Processor (MJ)

职位类别： 其它兼职类

Location: Shanghai/Shenzhen



Role and Responsibility:

-Architect and implement verification environment for complex IPs

-Work with design team and drive IP design into verification convergence 

-Develop scripting and infrastructure to support verification flow

-Build up re-usable and scalable verification IP library



Requirement:

-2 to 6 years design verification experience

-Good understanding of CPU or DSP architecture, memory/bus architecture and assembly -language for ARM or other architecture

-Deep understanding of design verification methodology

-Thorough knowledge of System Verilog and UVM

-Hands on experience on functional verification environment implementation, test case writing and RTL functional debug

-Experience in specification, creation, and debug of System Verilog/UVM constrained-random testbench

-Proficiency in scripting language such as Perl, TCL, Python

-Formal verification experience is a metric

-With excellent communication skill, teamwork and attention to details

• 年龄要求： 不限
• 语言要求：不限