Digital IC Design Engineer

职位类别： 其它兼职类

职责描述：

ASIC design engineer responsible for post RTL design flow including synthesis, timing closure, DFT and physical design flow. He or she will be responsible for block and/or chip level synthesis, timing closure, DFT, physical design, and integration.



任职要求：

MSEE w/ 5-8 year experience in developing and implementing ASIC products.

Must have good post-RTL experience including synthesis, timing analysis, and physical design. Good understanding of block and top-level physical timing closure. Flexible to move between all post-RTL designs activities as required. Able to perform custom placement and routing for mixed-signal designs.

Must be proficient in the following skills:

² Logic or physical synthesis using Synopsys or Cadence tools

² DFT generation and verification

² Static timing analysis using Primetime

² Physical design for 28nm and beyond

² Strong Perl and Tcl scripting skill

Highly desirable skills:

² Low power design

² Circuit level or custom design experience

² Floorplanning, clock-tree synthesis and power planning/analysis

² Signal integrity and physical verification

Good personal communication skills and team working spirit. Hardworking and motivated to be part of a highly competent design team.

• 年龄要求： 不限
• 语言要求：不限